View AK4384ET_4367196.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asahi kasei [ak4384] ms0176-e-01 2006/01 - 1 - general description the ak4384 offers the perfect mix for cost and performance based audio systems. using akm's multi bit architecture for its modulator the ak4384 delivers a wide dynamic range while preserving linearity for improved thd+n performance. the ak4384 integrates a combination of scf and ctf filters increasing performance for systems with excessive clock jitter. the 24 bit word length and 192khz sampling rate make this part ideal for a wide range of applications including dvd-audio. the ak4384 is offered in a space saving 16pin tssop package. features ? sampling rate ranging from 8khz to 192khz ? 128 times oversampling (normal speed mode) ? 64 times oversampling (double speed mode) ? 32 times oversampling (quad speed mode) ? 24-bit 8 times fir digital filter ? scf with high tolerance to clock jitter ? 2nd order analog lpf ? single ended output buffer ? digital de-emphasis for 32k, 44.1k and 48khz sampling ? soft mute ? digital attenuator (linear 256 steps) ? i/f format: 24-bit msb justified, 24/20/16-bit lsb justified or i 2 s ? master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (normal speed mode) 128fs, 192fs, 256fs or 384fs (double speed mode) 128fs, 192fs (quad speed mode) ? thd+n: -94db ? dynamic range: 106db ? power supply: 4.5 to 5.5v ? very small package: 16pin tssop (6.4mm x 5.0mm) lrc k bic k sdti a udio data interface mclk pdn ? modulator aoutl 8x interpolator scf lpf aoutr v dd v ss v com de-emphasis control p/s p interface clock divider smute/csn acks/ccl k dif0/cdti ? modulator 8x interpolator dzfr dzfl scf lpf at t at t 106db 192khz 24-bit 2ch ? dac ak4384
asahi kasei [ak4384] ms0176-e-01 2006/01 - 2 - ? ordering guide AK4384ET -20 +85 c 16pin tssop (0.65mm pitch) ak4384vt -40 +85 c 16pin tssop (0.65mm pitch) akd4384 evaluation board for ak4384 ? pin layout 1 mclk lrck bick smute/csn acks/cclk dif0/cdti top view 2 3 4 5 6 7 8 dzfl dzfr vss vdd vcom a outl a outr p/s 16 15 14 13 12 11 10 9 pdn sdti pin/function no. pin name i/o function 1 mclk i master clock input pin an external ttl clock should be input on this pin. 2 bick i audio serial data clock pin 3 sdti i audio serial data input pin 4 lrck i l/r clock pin 5 pdn i power-down mode pin when at ?l?, the ak4384 is in the power-down mode and is held in reset. the the ak4384 must be reset once upon power-up. smute i soft mute pin in parallel mode ?h?: enable, ?l?: disable 6 csn i chip select pin in serial mode acks i auto setting mode pin in parallel mode ?l?: manual setting mode, ?h?: auto setting mode 7 cclk i control data clock pin in serial mode dif0 i audio data interface format pin in parallel mode 8 cdti i control data input pin in serial mode 9 p/s i parallel/serial select pin (internal pull-up pin) ?l?: serial control mode, ?h?: parallel control mode 10 aoutr o rch analog output pin 11 aoutl o lch analog output pin 12 vcom o common voltage pin, vdd/2 normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 13 vss - ground pin 14 vdd - power supply pin 15 dzfr o rch data zero input detect pin 16 dzfl o lch data zero input detect pin note: all input pins except pull-up pin should not be left floating.
asahi kasei [ak4384] ms0176-e-01 2006/01 - 3 - absolute maximum ratings (vss=0v; note 1) parameter symbol min max units power supply vdd -0.3 6.0 v input current (any pins except for supplies) iin - 10 ma input voltage vind -0.3 vdd+0.3 v AK4384ET ta -20 85 c ambient operating temperature (powered applied) ak4384vt ta -40 85 c storage temperature tstg -65 150 c note: 1. all voltages with respect to ground. warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss=0v; note 1) parameter symbol min typ max units power supply vdd 4.5 5.0 5.5 v *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [ak4384] ms0176-e-01 2006/01 - 4 - analog characteristics (ta=25 c; vdd=5.0v; fs=44.1khz; bick=64fs; signal frequency=1khz; 24bit input data; measurement frequency=20hz 20khz; r l 5k ? ; unless otherwise specified) parameter min typ max units resolution 24 bits dynamic characteristics (note 3) fs=44.1khz bw=20khz 0dbfs -60dbfs -94 -42 -84 - db db fs=96khz bw=40khz 0dbfs -60dbfs -92 -39 - - db db thd+n fs=192khz bw=40khz 0dbfs -60dbfs -92 -39 - - db db dynamic range (-60dbfs with a-weighted) (note 4) 100 106 db s/n (a-weighted) (note 5) 100 106 db interchannel isolation (1khz) 90 100 db interchannel gain mismatch 0.2 0.5 db dc accuracy gain drift 100 - ppm/ c output voltage (note 6) 3.15 3.40 3.65 vpp load resistance (note 7) 5 k ? power supplies power supply current (vdd) normal operation (pdn = ?h?, fs 96khz) normal operation (pdn = ?h?, fs=192khz) power-down mode (pdn = ?l?) (note 8) 17 20 10 27 32 100 ma ma a notes: 3. measured by audio precision (system two). refer to the evaluation board manual. 4. 100db at 16bit data. 5. s/n does not depend on input bit length. 6. full-scale voltage (0db). output voltage scales with the voltage of vref, aout (typ.@0db) = 3.4vpp vdd/5. 7. for ac-load. 8. all digital inputs including clock pins (m clk, bick and lrck) are held vdd or vss.
asahi kasei [ak4384] ms0176-e-01 2006/01 - 5 - sharp roll-off filter characteristics (ta = 25 c; vdd = 4.5 5.5v; fs = 44.1khz; dem = off; slow = ?0?) parameter symbol min typ max units digital filter passband 0.05db (note 9) -6.0db pb 0 - 22.05 20.0 - khz khz stopband (note 9) sb 24.1 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay (note 10) gd - 19.3 - 1/fs digital filter + lpf frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.03 0.03 0.03 - - - db db db notes: 9. the passband and stopband frequencies scale with fs(system sampling rate). for example, pb=0.4535fs (@ 0.05db), sb=0.546fs. 10. the calculating delay time which occurred by digital filtering. this time is from setting the 16/24bit data of both channels to input register to the output of analog signal. slow roll-off filter characteristics (ta = 25 c; vdd = 4.5 ~ 5.5v; fs = 44.1khz; dem = off; slow = ?1?) parameter symbol min typ max units digital filter passband 0.04db (note 11) -3.0db pb 0 - 18.2 8.1 - khz khz stopband (note 11) sb 39.2 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay (note 10) gd - 19.3 - 1/fs digital filter + lpf frequency response 20.0khz 40.0khz 80.0khz fs=44.khz fs=96khz fs=192khz fr fr fr - - - +0.02/-5 +0.02/-4 +0.02/-5 - - - db db db note: 11. the passband and stopband frequencies scale with fs. for example, pb = 0.185fs (@ 0.04db), sb = 0.888fs. dc characteristics (ta=25 c; vdd=4.5 5.5v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (iout=-80a) low-level output voltage (iout=80a) voh vol vdd-0.4 - - - 0.4 v v input leakage current (note 12) iin - - 10 a note: 12. p/s pin has internal pull-up device, normally 100k ? .
asahi kasei [ak4384] ms0176-e-01 2006/01 - 6 - switching characteristics (ta=25 c; vdd=4.5 5.5v) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 2.048 40 11.2896 36.864 60 mhz % lrck frequency normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 60 120 45 48 96 192 55 khz khz khz % audio interface timing bick period normal speed mode double/quad speed mode bick pulse width low pulse width high bick rising to lrck edge (note 13) lrck edge to bick rising (note 13) sdti hold time sdti setup time tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns reset timing pdn pulse width (note 14) tpd 150 ns notes: 13. bick rising edge must not occur at the same time as lrck edge. 14. the ak4384 can be reset by bringing pdn= ?l?.
asahi kasei [ak4384] ms0176-e-01 2006/01 - 7 - ? timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr serial interface timing
asahi kasei [ak4384] ms0176-e-01 2006/01 - 8 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing tpd vil pdn power-down timing
asahi kasei [ak4384] ms0176-e-01 2006/01 - 9 - operation overview ? system clock the external clocks, which are required to operate the ak4384, are mclk, lrck and bick. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. there are two methods to set mclk frequency. in manual setting mode (acks = ?0?: register 00h), the sampling speed is set by dfs0/1(table 1). the frequency of mclk at each sampling speed is set automatically. (table 2~4).after exiting reset (pdn = ? ?), the ak4384 is in auto setting mode. in auto setting mode (acks = ?1?: default), as mclk frequency is detected automatically (table 5), and the internal master clock becomes the appropriate frequency (table 6), it is not necessary to set dfs0/1. in parallel mode, the sampling speed can be set by acks pin. the internal dfs0 anddfs1 bits are fixed to ?0?. therefore, when acks pin is ?l?, the ak4384 operates in normal speed mode. the ak4384 operates in auto setting mode at acks = ?h?. in parallel mode, the ak4384 does not support 128fs and 192fs of double speed mode. all external clocks (mclk,bick and lrck) should always be present whenever the ak4384 is in the normal operation mode (pdn= ?h?). if these clocks are not provided, the ak 4384 may draw excess current and may fall into unpredictable operation. this is because the device utilizes dynamic refreshed logic internally. the ak4384 should be reset by pdn= ?l? after threse clocks are provided. if the external cl ocks are not present, the ak4384 should be in the power-down mode (pdn= ?l?). after exiting reset at power-up etc., the ak4384 is in the power-down mode until mclk and lrck are input. dfs1 dfs0 sampling rate (fs) 0 0 normal speed mode 8khz~48khz default 0 1 double speed mode 60khz~96khz 1 0 quad speed mode 120khz~192khz table 1. sampling speed (manual setting mode) lrck mclk bick fs 256fs 384fs 512fs 768fs 1152fs 64fs 32.0khz 8.1920mhz 12.2880mhz 16.3840mhz 24.5760mhz 36.8640mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz n/a 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz n/a 3.0720mhz table 2. system clock example (normal speed mode @manual setting mode) lrck mclk bick fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 5.6448mhz 96.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 6.1440mhz table 3. system clock example (double sp eed mode @manual setting mode)
asahi kasei [ak4384] ms0176-e-01 2006/01 - 10 - lrck mclk bick fs 128fs 192fs 64fs 176.4khz 22.5792mhz 33.8688mhz 11.2896mhz 192.0khz 24.5760mhz 36.8640mhz 12.2880mhz table 4. system clock example (quad speed mode @manual setting mode) mclk sampling speed 512fs 768fs normal 256fs 384fs double 128fs 192fs quad table 5. sampling speed (auto setting mode: default) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz - - - - 16.3840 24.5760 36.8640 44.1khz - - - - 22.5792 33.8688 - 48.0khz - - - - 24.5760 36.8640 - normal 88.2khz - - 22.5792 33.8688 - - - 96.0khz - - 24.5760 36.8640 - - - double 176.4khz 22.5792 33.8688 - - - - - 192.0khz 24.5760 36.8640 - - - - - quad table 6. system clock example (auto setting mode) ? audio serial interface format data is shifted in via the sdti pin using bick and lrck input s. the dif0-2 as shown in table 7 can select five serial data modes. in all modes the serial data is msb-first, 2?s compliment format and is latched on the rising edge of bick. mode 2 can be used for 16/20 msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 sdti format bick figure 0 0 0 0 16bit lsb justified 32fs figure 1 1 0 0 1 20bit lsb justified 40fs figure 2 2 0 1 0 24bit msb justified 48fs figure 3 default 3 0 1 1 24bit i 2 s compatible 48fs figure 4 4 1 0 0 24bit lsb justified 48fs figure 2 table 7. audio data formats (serial mode) mode dif0 sdti format bick figure 2 0 24bit msb justified 48fs figure 3 3 1 24bit i 2 s compatible 48fs figure 4 table 8. audio data formats (parallel mode)
asahi kasei [ak4384] ms0176-e-01 2006/01 - 11 - sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3 2 1 0 15 14 ( 32fs ) ( 64fs ) 014 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 1. mode 0 timing sdti lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdti mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 8 23 23 8 figure 2. mode 1,4 timing lrck bick ( 64fs ) sdti 022 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 224 23 30 22 1 0don?t care 23 22 23 figure 3. mode 2 timing
asahi kasei [ak4384] ms0176-e-01 2006/01 - 12 - lrck bick ( 64fs ) sdti 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 224 23 25 22 1 0 don?t care 23 23 figure 4. mode 3 timing ? de-emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc = 50/15s) and is enabled or disabled with dem0 and dem1. in case of double speed and quad speed mode, the digital de-emphasis filter is always off. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 9. de-emphasis filter control (normal speed mode) ? output volume the ak4384 includes channel independent digital output volumes (att) with 256 levels at linear step including mute. these volumes are in front of the dac and can attenuate the input data from 0db to ?48db and mute. when changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. the transition time of 1 level and all 256 levels is shown in table 10. transition time sampling speed 1 level 255 to 0 normal speed mode 4lrck 1020lrck double speed mode 8lrck 2040lrck quad speed mode 16lrck 4080lrck table 10. att transition time
asahi kasei [ak4384] ms0176-e-01 2006/01 - 13 - ? zero detection the ak4384 has channel-independent zeros detect function. when the input data at each channel is continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to ?h?. dzf pin of each channel immediately goes to ?l? if input data of each channel is not zero after going dzf ?h?. if rstn bit is ?0?, dzf pins of both channels go to ?h?. dzf pin of both channels go to ?l? at 2~3/fs after rstn bit returns to ?1?. if dzfm bit is set to ?1?, dzf pins of both channels go to ?h? only when the input data at both channels are continuously zeros for 8192 lrck cycles. zero detect function can be disabled by dzfe bit. in this case, dzf pins of both cha nnels are always ?l?. dzfb bit can invert the polarity of dzf pin. ? soft mute operation soft mute operation is performed at digital domain. when the smute bit goes to ?1?, the output signal is attenuated by - during att_data att transition time (table 10) from the current att level. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit a ttenuation dzf pin att level - a out 8192/fs gd gd (1) (2) (3) (4) (1) notes: (1) att_data att transition time (table 10). for example, in normal speed mode, this time is 1020lrck cycles (1020/fs) at att_data=255. (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at each channel is continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to ?h?. dzf pin immediately goes to ?l? if input data are not zero after going dzf ?h?. figure 5. soft mute and zero detection
asahi kasei [ak4384] ms0176-e-01 2006/01 - 14 - ? system reset the ak4384 should be reset once by bringing pdn= ?l? upon power-up. the ak4384 is powered up and the internal timing starts clocking by lrck ? ? after exiting reset and power down state by mclk. the ak4384 is in the power-down mode until mclk and lrck are input. ? power-down the ak4384 is placed in the power-down mode by bringing pdn pin ?l? and the anlog outputs are floating (hi-z). figure 6 shows an example of the system timing at the power-down and power-up. normal operation internal state pdn power-down normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk, lrck, bick (1) (3) (6) dzfl/dzfr external mute (5) (3) (1) mute on (2) (4) don?t care notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs are floating (hi -z) at the power-down mode. (3) click noise occurs at the edge of pdn signal. this noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the power-down mode (pdn = ?l?). (5) please mute the analog output externally if the click noise (3) influences system application. the timing example is shown in this figure. (6) dzf pins are ?l? in the power-down mode (pdn = ?l?). figure 6. power-down/up sequence example
asahi kasei [ak4384] ms0176-e-01 2006/01 - 15 - ? reset function when rstn=0, dac is powered down but the internal register values are not initialized. the analog outputs go to vcom voltage and dzfl/dzfr pins go to ?h?. figure 7 shows the example of reset by rstn bit. internal state rstn bit digital block power-down normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (3) dzf (3) (1) (2) normal operation 2/fs(5) internal rstn bit 2~3/fs (6) 3~4/fs (6) don?t care (4) notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs go to vcom voltage (vdd/2). (3) click noise occurs at the edges(? ?) of the internal timing of rstn bit. this noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the reset mode (rstn = ?l?). (5) dzf pins go to ?h? when the rstn bit becomes ?0?, and go to ?l? at 2/fs after rstn bit becomes ?1?. (6) there is a delay, 3~4/fs from rstn bit ?0? to the in ternal rstn bit ?0?, and 2~3/fs from rstn bit ?1? to the internal rstn ?1?. figure 7. reset sequence example
asahi kasei [ak4384] ms0176-e-01 2006/01 - 16 - ? mode control interface some function of the ak4384 can be controlled by pins (parallel control mode) shown in table 11. the serial control interface is enabled by the p/s pin = ?l?. internal registers may be written by 3-wire p interface pins, csn, cclk and cdti. the data on this interface consists of chip address (2bits, c1/0; fixed to ?01?), read/write (1bit; fixed to ?1?, write only), register address (msb first, 5bits) and contro l data (msb first, 8bits). ak4384 latches the data on the rising edge of cclk, so data should clocked in on the falling edge. the writing of data becomes valid by csn ? ?. the clock speed of cclk is 5mhz (max). function parallel mode serial mode double sampling mode at 128/192fs x o de-emphasis x o smute o o zero detection x o 16/20/24bit lsb justified format x o table 11. . function list (o: available, x: not available) pdn = ?l? resets the registers to their default values. when the state of p/s pin is changed, the ak4384 should be reset by pdn= ?l?. the internal timing circuit is reset by rstn bit, but the registers are not initialized. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (fixed to ?01?) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 8. control i/f timing *the ak4384 does not support the read command and chip address. c1/0 and r/w are fixed to ?011? *when the ak4384 is in the power down mode (pdn = ?l?) or the mclk is not provided, writing into the control register is inhibited. ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks 0 0 dif2 dif1 dif0 pw rstn 01h control 2 dzfe dzfm slow dfs1 dfs0 dem1 dem0 smute 02h control 3 0 0 0 invl invr dzfb 0 0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 notes: for addresses from 05h to 1fh, data must not be written. when pdn pin goes ?l?, the registers are initialized to their default values. when rstn bit goes ?0?, the only internal timing is reset and the registers are not initialized to their default values. all data can be written to the register even if pw or rstn bit is ?0?.
asahi kasei [ak4384] ms0176-e-01 2006/01 - 17 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks 0 0 dif2 dif1 dif0 pw rstn default 1 0 0 0 1 0 1 1 rstn: internal timing reset control 0: reset. all registers are not initialized. 1: normal operation when mclk frequency or dfs changes, the click noise can be reduced by rstn bit. pw: power down control 0: power down. all registers are not initialized. 1: normal operation dif2-0: audio data interface formats (see table 7) initial: ?010?, mode 2 acks: master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected automatically at acks bit ?1?. in this case, the setting of dfs1-0 are ignored. when this bit is ?0?, dfs1-0 set the sampling speed mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 dzfe dzfm slow dfs1 dfs0 dem1 dem0 smute default 0 0 0 0 0 0 1 0 smute: soft mute enable 0: normal operation 1: dac outputs soft-muted dem1-0: de-emphasis response (see table 9) initial: ?01?, off dfs1-0: sampling speed control 00: normal speed 01: double speed 10: quad speed when changing between normal/double speed mode and quad speed mode, some click noise occurs. slow: slow roll-off filter enable 0: sharp roll-off filter 1: slow roll-off filter dzfe: data zero detect enable 0: disable 1: enable zero detect function can be disabled by dzfe bit ?0 ?. in this case, the dzf pins of both channels are always ?l?.
asahi kasei [ak4384] ms0176-e-01 2006/01 - 18 - dzfm: data zero detect mode 0: channel separated mode 1: channel anded mode if the dzfm bit is set to ?1?, the dzf pins of both channels go to ?h? only when the input data at both channels are continuously zeros for 8192 lrck cycles. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 0 0 0 invl invr dzfb 0 0 default 0 0 0 0 0 0 0 0 dzfb: inverting enable of dzf 0: dzf goes ?h? at zero detection 1: dzf goes ?l? at zero detection invr: inverting lch output polarity 0: normal output 1: inverted output invl: inverting rch output polarity 0: normal output 1: inverted output addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 default 1 1 1 1 1 1 1 1 att = 20 log 10 (att_data / 255) [db] 00h: mute
asahi kasei [ak4384] ms0176-e-01 2006/01 - 19 - system design figure 9 and 10 show the system connection diagram. an evaluation board (akd4384) is available in order to allow an easy study on the layout of a surrounding circuit. mclk 1 bick 2 sdti 3 lrck 4 pdn 5 smute 6 a cks 7 dif0 8 dzfl 16 dzfr 15 vdd 14 vss 13 vcom 12 aoutl 11 aoutr 10 p/s 9 master clock mode setting ak4384 fs 24bit audio data reset & power down 64fs 10u 0.1u + rch out lch out analog ground digital ground lch mute rch mute a nalog supply 5v + 10u figure 9. typical connection diagram (parallel mode) mclk 1 bick 2 sdti 3 lrck 4 pdn 5 csn 6 cclk 7 cdti 8 dzfl 16 dzfr 15 vdd 14 vss 13 vcom 12 aoutl 11 aoutr 10 p/s 9 master clock micro- controller ak4384 fs 24bit audio data reset & power down 64fs 10u 0.1u + rch out lch out analog ground digital ground lch mute rch mute a nalog supply 5v + 10u figure 10. typical connection diagram (serial mode) notes: - lrck = fs, bick = 64fs. - when aout drives some capacitive load, some resistor should be added in series between aout and capacitive load. - all input pins except pull-up pin should not be left floating.
asahi kasei [ak4384] ms0176-e-01 2006/01 - 20 - 1. grounding and power supply decoupling vdd and vss are supplied from analog supply and should be separated from system digital supply. decoupling capacitor, especially 0.1 f ceramic capacitor for high frequency should be placed as near to vdd as possible. the differential voltage between vdd and vss pins set the analog output range. 2. analog outputs the analog outputs are single-ended and centered around the vcom voltage. the output signal range is typically 3.40vpp (typ@vdd=5v). the phase of the analog outputs can be inverted channel independently by invl/invr bits. the internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. the output voltage is a positive full scale for 7fffffh (@24bit) and a negative full scale for 800000h (@24bit). the ideal output is vcom voltage for 000000h (@24bit). dc offsets on analog outputs are eliminated by ac coupling since analog outputs have dc offsets of vcom + a few mv. figure 11 shows an example of the external lpf with 2vrms output. 820p 3.3k 1.5k 1.8k 820p +vop 2.2k -vop aout 22u fc=111.8khz, q=0.714, g=-0.04db at 40khz analog out 10k figure 11. external 2 nd order lpf circuit example (using op-amp with dual power supplies)
asahi kasei [ak4384] ms0176-e-01 2006/01 - 21 - package 0-10 detail a seating plane 0.10 0.17 0.1 0.65 *5.0 0.1 1.05 0.05 a 1 8 9 16 16 p in tssop ( unit: mm ) *4.4 0.1 6.4 0.2 0.5 0.2 0.1 0.1 note: dimension "*" does not include mold flash. 0.13 m ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder(pb free) plate
asahi kasei [ak4384] ms0176-e-01 2006/01 - 22 - marking (ak4384vt) akm 4384vt xxyyy 1) pin #1 indication 2) date code : xxyyy (5 digits) xx: lot# yyy: date code 3) marketing code : 4384vt 4) asahi kasei logo
asahi kasei [ak4384] ms0176-e-01 2006/01 - 23 - marking (AK4384ET) akm 4384et xxyyy 5) pin #1 indication 6) date code : xxyyy (5 digits) xx: lot# yyy: date code 7) marketing code : 4384et 8) asahi kasei logo
asahi kasei [ak4384] ms0176-e-01 2006/01 - 24 - revision history date (yy/mm/dd) revision reason page contents 02/09/11 00 first edition 2 ordering guide AK4384ET was added. 06/01/11 01 spec addition 23 marking AK4384ET was added. important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulati ons of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK4384ET

	To Download AK4384ET Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .